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PRELIMINARY
FEMTOCLOCKTM CRYSTAL-TO-HCSL CLOCK GENERATOR
ICS841664I
GENERAL DESCRIPTION
The ICS841664I is an optimized sRIO clock IC S generator and member of the HiPerClocksTM family HiPerClockSTM of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to generate 125MHz and 156.25MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter sRIO clock signals. Designed for telecom, networking and industrial applications, the ICS841664I can also drive the high-speed sRIO SerDes clock inputs of communication processors, DSPs, switches and bridges.
FEATURES
* Four differential HCSL clock outputs: configurable for sRIO (125MHz or 156.25MHz) clock signals One REF_OUT LVCMOS/LVTTL clock output * Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input * Supports the following output frequencies: 125MHz or 156.25MHz * VCO: 625MHz * PLL bypass and output enable * RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz): 0.35ps (typical) @ 125MHz * Full 3.3V power supply mode * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
XTAL_IN
PIN ASSIGNMENT
1
OSC
XTAL_OUT REF_IN Pulldown REF_SEL Pulldown
0
QA0 nQA0
FemtoClock PLL
1
VCO = 625MHz
0
/NA
QA1 nQA1
M = /25
QB0 nQB0
/NB
IREF
BYPASS Pulldown FSEL[0:1] Pulldown MR/nOE Pulldown
QB1 nQB1
VDD REF_OUT GND QA0 nQA0 VDDOA GND QA1 nQA1 nREF_OE BYPASS REF_IN REF_SEL VDDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
IREF FSEL0 FSEL1 QB0 nQB0 VDDOB GND QB1 nQB1 MR/nOE VDD XTAL_IN XTAL_OUT GND
ICS841664I
28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm package body G Package Top View
REF_OUT nREF_OE Pullup
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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TABLE 1. PIN DESCRIPTIONS
Number 1, 18 2 3, 7, 15, 22 4, 5 , 8, 9 6 10 11 12 13 14 16, 17 Name VDD REF_OUT GND QA0, nQA0, QA1, nQA1 VDDOA nREF_OE BYPASS REF_IN REF_SEL VDDA XTAL_OUT, XTAL_IN MR/nOE nQB1, QB1 nQB0, QB0 VDDOB FSEL1, FSEL0 IREF Power Output Power Ouput Power Input Input Input Input Power Input Pullup Pulldown Pulldown Pulldown Type Description Core supply pins. LVCMOS/LVTTL reference frequency clock output. Power supply ground. Differential Bank A output pairs. HCSL interface levels. Output supply pin for Bank A outputs. Active low REF_OUT enable/disable. See Table 3E. LVCMOS/LVTTL interface levels. Selects PLL operation/PLL bypass operation. See Table 3C. LVCMOS/LVTTL interface levels. LVCMOS/LVTTL PLL reference clock input. Reference select. Selects the input reference source. See Table 3B. LVCMOS/LVTTL interface levels. Analog supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. (PLL reference.) Active HIGH master reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are in high impedance (HiZ). When logic LOW, the internal dividers and the outputs are enabled. See Table 3D. LVCMOS/LVTTL interface levels. Differential Bank B output pairs. HCSL interface levels. Output supply pin for Bank B outputs. Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
19 20, 21 24, 25 23 26, 27 28
Input
Pulldown
Output Power Input Output
HCSL current reference resistor output. A fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode QXx/nQXx clock outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN Parameter Input Capacitance Power Dissipation Capacitance Input PullupResistor Input Pulldown Resistor VDD, VDDOA, VDDOB = 3.465V Test Conditions Minimum Typical 4 18 51 51 Maximum Units pF pF k k
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TABLE 3A. FSELX FUNCTION TABLE (fref = 25MHZ)
Inputs FSEL1 0 0 1 1 FSEL0 0 1 0 1 M 25 25 25 25 Outputs Frequency Settings QA0:1/nQA0:1 VCO/5 (125MHz) VCO/5 (125MHz) VCO/5 (125MHz) VCO/4 (156.25MHz) QB0:1/nQB0:1 VCO/5 (125MHz) VCO/4 (156.25MHz) QB0:1 = L, nQB0:1 = H VCO/4 (156.25MHz)
TABLE 3B. REF_SEL FUNCTION TABLE
Input REF_SEL 0 1 Input Reference XTAL REF_IN
TABLE 3C. BYPASS FUNCTION TABLE
Input BYPASS 0 1 PLL Configuration PLL on PLL bypassed (QA, QB = fref/N)
NOTE 1: Asynchr. function (may cause output glitch).
TABLE 3D. MR/nOE FUNCTION TABLE
Input MR/nOE 0 1 FunctionNOTE 1 Outputs enabled Device reset, outputs disabled (Low)
NOTE 1: Asynchr. function (may cause output glitch).
TABLE 3E. nREF_OE FUNCTION TABLE
Input nREF_OE 0 1 FunctionNOTE 1 REF_OUT enabled REF_OUT disabled (high impedance)
NOTE 1: Asynchr. function (may cause output glitch).
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO_X + 0.5V 64.5C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDOA, VDDOB IDD IDDA IDDOA, IDDOB Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.15 3.135 Typical 3.3 3.3 3.3 70 15 75 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage REF_IN, REF_SEL, BYPASS, MR/nOE, FSEL0, FSEL1 nREF_OE REF_IN, REF_SEL, BYPASS, MR/nOE, FSEL0, FSEL1 nREF_OE VOH VDD = VIN = 3.465 V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0. 8 15 0 5 Units V V A A A A V 0.775 V
Input High Current
IIL
Input Low Current
Ouput High Voltage; 2.275 REF_OUT VDD = 3.465V NOTE 1 Ouput Low Voltage; REF_OUT VDD = 3.465V VOL NOTE 1 Output Impedance REF_OUT VDD = 3.465V 20 ZOUT NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information Section, Output Load Test Circuit diagram.
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TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. Test Conditions Minimum Typical 25 50 7 0.1 Maximum Units MHz pF mW Fundamental
TABLE 6A. LVCMOS AC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fMAX tR / tF o dc Output Frequency Output Duty Cycle REF_OUT 20% to 80% Output Rise/Fall Time Test Conditions Minimum Typical 25 1 50 Maximum Units MHz ns %
TABLE 6B. HCSL AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fMAX Output Frequency Test Conditions VCO/5 VCO/4 125MHz, (1.875MHz - 20MHz) 156.25MHz, (1.875MHz - 20MHz) Minimum Typical 125 156.25 0.35 0.35 Maximum Units MHz MHz ps ps ps 1 660 -150 0.3 -0.3 0.2 700 850 150 0.3 -0.3 ms mV mV V V V
tjit(O)
RMS Phase Jitter (Random); NOTE 1 Output Skew; NOTE 2, 3 PLL Lock Time Voltage High Voltage Low Max. Voltage, Overshoot Min. Voltage, Undershoot Ringback Voltage QAx/nQAx, QBx/nQBx
tsk(o)
tL VHIGH VLOW VOVS VUDS Vrb VCROSS
Absolute Crossing Voltage 250 550 mV Total Variation of VCROSS over all 140 mV VCROSS edges QAx/nQAx, measured between tR / tF Output Rise/Fall Time 350 ps QBx/nQBx 0.175V to 0.525V Rise/Fall Time Variation 125 ps tR /tF QAx/nQAx, odc Output Duty Cycle 50 % QBx/nQBx NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All specifications are taken at 125MHz and 156.25MHz. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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TYPICAL PHASE NOISE AT 125MHZ AT 3.3V
sRIO Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.35ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
TYPICAL PHASE NOISE AT 156.25MHZ AT 3.3V
sRIO Filter 156.25MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.35ps (typical)
Phase Noise Result by adding an sRIO Filter to raw data OFFSET FREQUENCY (HZ)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding an sRIO Filter to raw data OFFSET FREQUENCY (HZ)
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
3.3V5% 3.3V5%, 1.65V5% 1.65V5% VDD, VDDOA, VDDOB 33 VDDA 50 VDDA 50 Measurement Point 50 Measurement Point
VDD Qx
SCOPE
HSCL
33 GND 475 0V 50
LVCMOS
GND
-1.65V5%
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nQx Qx nQy Qy
tsk(o)
f1 Offset Frequency f2
Noise Power
Phase Noise Mask
RMS Jitter = Area Under the Masked Phase Noise Plot
HCSL OUTPUT SKEW
V
RMS PHASE JITTER
nQA0, nQA1, nQB0, nQB1 QA0, QA1, QB0, QB1
DDO
REF_OUT t PW
t
2
t PW
t
PERIOD
PERIOD
odc =
t PW t PERIOD
odc =
t PW t PERIOD
x 100%
x 100%
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
HCSL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQA0, nQA1, nQB0, nQB1
80% 20% tR
80% 20% tF
QA0, QA1, 0.175V QB0, QB1
0.525V
0.525V VSW I N G
REF_OUT
0.175V tR tF
LVCMOS OUTPUT RISE/FALL TIME
HCSL OUTPUT RISE/FALL TIME
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841664I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDOA and VDDOB should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS841664I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p
FIGURE 2. CRYSTAL INPUt INTERFACE
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LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the
VDD VCC
series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD VCC
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_IN INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_IN to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
HCSL OUTPUTS All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS OUTPUT The unused LVCMOS output can be left floating. We recommend that there is no trace attached.
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RECOMMENDED TERMINATION
Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50 impedance.
FIGURE 4A. RECOMMENDED TERMINATION
Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50 impedance.
FIGURE 4B. RECOMMENDED TERMINATION
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SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS841664I application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. One example of HCSL and one example of LVCMOS terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin.
FIGURE 5. ICS841664I SCHEMATIC LAYOUT
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS841664I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841664I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and HCSL Output Power Dissipation * Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V * (70mA + 15mA) = 294.5mW * Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 44.5mW = 178mW LVCMOS Output Power Dissipation
*
Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDD)2 = 18pF * 25MHz * (3.465V)2 = 5.40mW per output
Total Power Dissipation * Total Power = Power (core) + Power (Outputs) + Total Power (25MHz) = 294.5mW + 178mW + 5.4mW = 477.9mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 64.5C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.478W * 64.5C/W = 115.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 28-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 64.5C/W
1
60.4C/W
2.5
58.5C/W
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3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6.
VDD
IOUT = 17mA
VOUT RREF =
475 1%
RL 50
IC
FIGURE 6. HCSL DRIVER CIRCUIT
AND TERMINATION
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX - VOUT ) * IOUT since VOUT = IOUT * RL Power = (VDD_MAX - IOUT * RL) * IOUT = (3.465V - 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW
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RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
28 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 64.5C/W
1
60.4C/W
2.5
58.5C/W
TRANSISTOR COUNT
The transistor count for ICS841664I is: 2954
PACKAGE OUTLINE
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP
AND
DIMENSIONS
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -6.00 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 9.60 8.10 BASIC 6.20 Millimeters Minimum 28 1.20 0.15 1.05 0.30 0.20 9.80 Maximum
Reference Document: JEDEC Publication 95, MO-153
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TABLE 10. ORDERING INFORMATION
Part/Order Number 841664AGI 841664AGIT 841664AGILF 841664AGILFT Marking ICS841664AGI ICS841664AGI ICS841664AGILF ICS841664AGILF Package 28 Lead TSSOP 28 Lead TSSOP 28 Lead "Lead-Free" TSSOP 28 Lead "Lead-Free" TSSOP Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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www.IDT.com
For Sales
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For Tech Support
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Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
(c) 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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